Polyphase filtering designs for FPGA provides performance boost for DSTO’s advanced receiver design.
April 10, 2006 (Press Release) --
RF Engines (RFEL), the experts in signal processing for FPGA, have been awarded a contract by Australia’s Defence Science and Technology Organisation (DSTO), for the provision of high performance digital filter designs. The designs, which form a key role in an advanced receiver systemsi, build on RFEL’s existing portfolio of signal processing intellectual property (IP), and deliver high quality filtering of wideband signals in real-time.
RFEL will provide DSTO with two filter designs, each based on frequency domain filtering techniques using the polyphase DFT. The first design will support a continuous complex sample rate of 200 MHz with 512 frequency domain weights, whilst the second design will support complex samples rates over 150 MHz with 4096 weights. The filter shapes are fully reprogrammable, and can be changed whilst the filter is running without loss of data.
Both designs are targeted at the Altera EP1S80 FPGA, a relatively small device for the level of performance being achieved.
“We are delighted that DSTO have selected RF Engines’ signal processing technology for this leading edge development,” said John Summers, RF Engines’ CEO. “It is a further example of our system design capabilities, and shows how we are able to provide rapid and cost-effective solutions to the most demanding signal processing challenges.”
Frequency Domain Filtering
Frequency domain techniques permit efficient implementation of traditional FIR filter functionality and are based on an analysis stage to convert the incoming signal to the frequency domain, and a synthesis stage to convert back to the time domain. The actual filtering process takes place in the frequency domain where it can be performed very efficiently.
The analysis-synthesis “pair” is typically implemented with a Fast Fourier Transform (FFT) and an Inverse FFT. However, for this contract, RF Engines will be using the Polyphase DFT, which can be considered as a superior replacement to the FFT since it provides far greater frequency isolation between frequency bins for the same transform length. This feature is particularly useful in a filter design, since it allows efficient implementation of very sharp transition bands, and hence greater filter performance for a given silicon resource budget.
For comparative purposes, the polyphase filter design with 4096 frequency domain weights will provide performance equivalent to a FIR filter with 16K taps. At the sample rates required by DSTO, this is well beyond the scope of a single FPGA implementation if attempted with traditional time domain convolution techniques.
Modelling
This work follows on from an initial study phase, in which RFEL was contracted by DSTO to investigate the feasibility of the filter implementation, and to produce bit true Matlab models of the filters. “We find that producing accurate simulation models is a crucial step in our design flow, since it allows customers to test out the design prior to the implementation stage, dramatically reducing any risk”, added John Summers.
RFEL will provide DSTO with two filter designs, each based on frequency domain filtering techniques using the polyphase DFT. The first design will support a continuous complex sample rate of 200 MHz with 512 frequency domain weights, whilst the second design will support complex samples rates over 150 MHz with 4096 weights. The filter shapes are fully reprogrammable, and can be changed whilst the filter is running without loss of data.
Both designs are targeted at the Altera EP1S80 FPGA, a relatively small device for the level of performance being achieved.
“We are delighted that DSTO have selected RF Engines’ signal processing technology for this leading edge development,” said John Summers, RF Engines’ CEO. “It is a further example of our system design capabilities, and shows how we are able to provide rapid and cost-effective solutions to the most demanding signal processing challenges.”
Frequency Domain Filtering
Frequency domain techniques permit efficient implementation of traditional FIR filter functionality and are based on an analysis stage to convert the incoming signal to the frequency domain, and a synthesis stage to convert back to the time domain. The actual filtering process takes place in the frequency domain where it can be performed very efficiently.
The analysis-synthesis “pair” is typically implemented with a Fast Fourier Transform (FFT) and an Inverse FFT. However, for this contract, RF Engines will be using the Polyphase DFT, which can be considered as a superior replacement to the FFT since it provides far greater frequency isolation between frequency bins for the same transform length. This feature is particularly useful in a filter design, since it allows efficient implementation of very sharp transition bands, and hence greater filter performance for a given silicon resource budget.
For comparative purposes, the polyphase filter design with 4096 frequency domain weights will provide performance equivalent to a FIR filter with 16K taps. At the sample rates required by DSTO, this is well beyond the scope of a single FPGA implementation if attempted with traditional time domain convolution techniques.
Modelling
This work follows on from an initial study phase, in which RFEL was contracted by DSTO to investigate the feasibility of the filter implementation, and to produce bit true Matlab models of the filters. “We find that producing accurate simulation models is a crucial step in our design flow, since it allows customers to test out the design prior to the implementation stage, dramatically reducing any risk”, added John Summers.
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