STANFORD, CALIF. --Sony Details PSP Chip Specs(PlayStation Portable game player )

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(Free-Press-Release.com) June 17, 2007 -- The chipset's designer did not comment, however, on the reasons for the PSP's delay. Sony has already said that the PSP will not ship in the U.S. until early 2005, and reports have surfaced that software makers don't believe the handheld will be released here until June 2005. Sony will ship the PSP in Japan later this year.

Not only will the PSP signal a new round in the console wars by challenging the established Nintendo Game Boy and new Nintendo DS, but the player will also begin the introduction of 3D-dedicated game into the handheld space.

The PSP will be based around four key blocks: the main CPU core, the media engine, the dedicated graphics processor, and the "Virtual Mobile engine," a reconfigurable assistant chip that will also be used in Sony's Walkman portable music player to conserve battery life. At press time, it wasn't clear whether each block would be integrated or broken out into a separate chip.


Some of the basic capabilities of the PSP player have already been disclosed. The game player will include a 4.3-inch widescreen TFT LCD, will contain a lithium-ion battery, and process AAC and MP3 music and AVC/@MP for pictures and movies. Games and other content will be stored on a 1.8-Gbyte UMD optical disc. The PSP is said to measure 70mm x 74mm x 23mm, and weigh 260 grams.

In a presentation at the Hot Chips conference here Tuesday, designer Masanobu Okabe described further details of the PSP chipset, which the company concealed with the non-specific title: "A 90-nm embedded DRAM single-chip LSI with a 3D graphics H.264 codec engine and a reconfigurable processor".

Sony Computer Entertainment executives said in May that the PSP would be powered by a MIPS R4000 embedded CPU. Okabe said Tuesday that the CPU will run at speeds up to 333-MHz, with a bus that can run at speeds up to 166-MHz, depending upon the application load. In low-load situations, Okabe said, the chip will power down unused blocks. The entire chip will total 6 million gates and an undisclosed amount of transistors. Sony will fabricate the chip in a 7-layer, copper-enhanced 90-nanometer process.

To save power, the chip core's voltage will range between 0.8 and 1.2 volts. Okabe declined to disclose the average power consumption of the chip or the 3D engine, claiming that the power will vary depending on the application.

The host CPU block will also contain a security sub-block designed to protect data and help prevent hacking the PSP, its games, or the stored data.

Okabe's presentation of the I/O also contained some unexpected surprises. Early disclosures of the PSP indicated that the player would be capable of communicating via 802.11b WiFi. The only I/O functions Okabe described were USB 2.0 and Memory Stick, Sony's small-form-factor flash memory format.

The PSP's graphics engine will feature a 512-bit interface, Okabe said, pushing 664 million pixels or 35 million polygons per second.